1. Field of the Invention
The present invention relates to a highly energy-efficient processor executing logic operations, and more particularly, to a processor having a structure that employs 2-stage dynamic voltage scaling (DVS) and a sleep mode, and ensures high energy efficiency. In addition, the present invention can be efficiently used in embedded processor architecture.
2. Discussion of Related Art
Processors can be classified into a single chip processor such as a central processing unit (CPU) used in a personal computer (PC), and an embedded processor used for a configuration block in a system on chip (SoC) such as various chips for control and smart cards. Embedded processors (micro processor unit (MPU)/micro controller unit (MCU)/digital signal processor (DSP)) are widely used for arithmetic and signal processing. In general, an embedded processor is a core block in a SoC that transforms and processes a signal by fetching, decoding and executing instructions, and executes operations of reading and writing the processed signal. As the degree of integration of highly functionalized embedded processors increases, so do power consumption and heat radiation.
In this patent specification, energy efficiency is defined as “performance/total power”. More specifically, with respect to an embedded processor, energy efficiency equals information processing/transformation capability divided by power consumption, and its units are million instructions per second (MIPS)/mW or millions of operations per second (MOPS)/mW. MIPS are general units for expressing performance and indicate how many millions of instructions can be processed per second. When the performance of an embedded processor is improved and the power consumption decreases, high energy efficiency can be achieved.
In general, power consumption is proportional to the square of an applied power supply voltage. Decrease of the power supply voltage is the most effective method for reducing power consumption, but a low power supply voltage increases a delay time, thereby decreasing the performance of a processor. Thus, a parallel-pipeline structure is widely used to improve the performance of an embedded processor. A typical parallel-pipeline structure is a single instruction multiple data (SIMD) structure transforming and processing several data in response to one instruction.
A DVS technique has the characteristic of dynamically reducing a power supply voltage, and can minimize performance deterioration caused while the power supply voltage is reduced by properly adjusting a transition from a reduced supply voltage Vdd1 to a normal supply voltage Vdd and vice versa.
FIG. 1 is a block diagram of a conventional SIMD structure of an embedded processor using a single power supply voltage. In the processor, performance is improved, but power consumption increases due to increase of hardware. Consequently, energy efficiency decreases.
FIG. 2 is a block diagram of a conventional embedded processor using multiple power supply voltages. In the processor, it is possible to reduce power consumption by properly using the multiple power supply voltages. However, a level shifter block adjusting a supply voltage level upon interfacing between blocks should be added because of the different power supply voltages. In some cases, the energy efficiency, i.e., “performance/total power”, may be lower than in a single supply voltage processor because of performance decrease caused by low driving voltage and level adjustment.